Symposium : M
More than Moore: Novel materials approaches for functionalized Silicon based Microelectronics
|Session 9 : Max Lemme|
|08:30||Hf and Zr –based very high dielectric constant oxides for logic and memory applications.|
Authors : C. Wiemer
Affiliations : Laboratorio MDM, IMM-CNR, Via C. Olivetti 2, 20864 Agrate Brianza, (MB), Italy
Resume : The scaling of semiconductor devices, as well as the research on innovative memories, require the tailoring of novel functional materials. Within transition metal oxides, Hf and Zr –based ones have been the most promising due to their compatibility with Silicon and high-mobility substrates. Recently, it has been demonstrated that the dielectric properties of HfO2 and ZrO2 can be tailored by doping with different elements ranging from Al to lanthanides. Moreover, the density of oxygen vacancies can also be influenced by the dopant element, therefore, these oxides might also be promising for resistive switching applications. We present here recent results on the structural and electrical properties of doped HfO2 and ZrO2 grown by atomic layer deposition. The crystallographic ordering of the ternary oxides is strongly dependent on the percentage of the dopant element. Detailed X-ray diffraction analysis, also performed using synchrotron radiation, as well as extended X-ray absorption fine structure measurements have elucidated the peculiar nature of the structural ordering of Er-doped HfO2 for different Er atomic percentages. The dependence of the dielectric constant on the crystallographic phase has been also extensively evaluated in some cased by dedicated density functional theory calculations. The integration of these doped oxides on high mobility substrates such as InGaAs and Ge have been pursued, and promising results have been obtained.
|09:00||Evaluation and modelling of lanthanum diffusion in TiN/La2O3/HfSiON/SiO2/Si high-k stacks|
Authors : Z. Essa*, C. Gaumer*, A. Pakfar**, M. Gros-Jean*, M. Juhel*, P. Boulenc*, and C. Tavernier*
Affiliations : *STMicroelectronics Crolles France **GlobalFoundries Dresden Germany
Resume : Lanthanum oxide (La2O3) capping layers have been extensively studied in the high-k metal gate technology because of their ability to reduce the threshold voltage (Vt) of n-type Metal Oxide Semiconductor Transistors. The Vt shift is due to dipoles formation at the interface between the high-k and its pedestal SiO2 interfacial layer (IL). Dipoles formation occurs during the high temperature spike anneal used for dopant activation. They have been showed to consist of lanthanum silicate (LaSiO), resulting from La diffusion through the high-k, from the capping layer to the IL. Literature results based on advanced process conditions involve ultra-thin HfSiON and SiO2 layers (< 2 nm) where the La diffusion mechanism is very difficult to investigate. In this study, poly-Si/TiN/La2O3/High-k/SiO2/Si gate stacks with thick high-k (HfSiO2 and HfSiON) and thick oxide IL were used. Samples were annealed at different temperatures and times in order to fine characterize the interaction mechanisms of La with the gate stack layers. Time of Flight Secondary Ion Mass Spectrometry (ToF-SIMS) measurements performed on these samples show a time diffusion saturation of La in the high-k in agreement with La front immobilization due to LaSiO formation at the high-k/IL interface. Based on the SIMS data, a Technology Computer Aided Design (TCAD) diffusion model including La time diffusion saturation effect was developed for the first time. La diffusivity both in HfSiON and SiO2 could thus be extracted.
|09:15||Effect of composition on the bandgap width in insulating niobate NbxMeyOz (Me=Ta or Gd) nano-layers|
Authors : W. C. Wang1, H. Y. Chou1, M. Badylevich2, T. Blomberg3, Ch. Wenger4, D. Dewulf5, A. Hardy5, M. K. Van Bael¬5,6, J. A. Kittl,7 and V. V. Afanas’ev1
Affiliations : 1. Department of Physics and Astronomy, University of Leuven, Celestijnenlaan 200D, B-3001 Leuven, Belgium 2. Present affiliation: Light and Lighting Laboratory, Catholic University College Gent, Gebroeders Desmetstraat 1, B-9000 Gent, Belgium 3. ASM Microchemistry Ltd., V?uerin katu 12 A, 00560 Helsinki, Finland 4. IHP, Im Technologiepark 25, Frankfurt 15236, Germany 5. Hasselt University, Inorganic and Physical Chemistry-IMO, Agoralaan Building D, B-3590, Diepenbeek, Belgium 6. IMEC div IMOMEC, Agoralaan Building D, B-3590 Diepenbeek, Belgium 7. IMEC, Kapeldreef 75, B-3001 Leuven, Belgium
Resume : Impact of composition and crystallinity on the bandgap width (Eg) of atomic layer deposited NbxTayOz and sol-gel derived NbxGdyOz thin insulating layers on silicon was investigated using combination of spectroscopic ellipsometry, internal photoemission and photoconductivity (PC) techniques. As compared to pure Ta2O5 (Eg=4.4 eV) and Nb2O5 (Eg=3.4 eV), with the Ta/(Ta Nb) ratio in NbxTayOz decreasing from 68.4 % to 10.7 %, the Eg changes from 4.3 to 3.5 eV in amorphous films and from 4.1 to 3.3 eV in the layers crystallized by a post-deposition annealing. This suggests the development of a phase with the abnormally narrow gap though, in the case of NbxTayOz layers with Ta/(Ta Nb)=41.9 % and Ta/(Ta Nb) =10.7 %, the additional PC threshold found at ~4.0 eV suggests the possible presence of a high density of electron states corresponding to the elemental oxide sub-networks. When admixing a wider-gap oxide Gd2O3 to Nb2O5, the gap width is found to increase from 4.1 eV in Gd/(Gd Nb)=0.16 to 5.4 eV in pure Gd2O3, suggesting no anomalous gap narrowing. We hypothesize that the gap narrowing encountered in NbxTayOz layers may be caused by reduction of the oxidation state of some of the Nb cations while Gd seems to stabilize the wide gap Nb2O5 sub-network.
|09:30||Properties of Atomic Layer Deposited Pt/SrTiO3/Pt Metal-Insulator-Metal Capacitors|
Authors : M. Lukosius1, T. Blomberg2, D. Walczyk1, G. Ruhl3, and Ch. Wenger1
Affiliations : 1IHP, Im Technologiepark 25, 15236 Frankfurt (Oder), Germany 2ASM Microchemistry Ltd., Väinö Auerin katu 12 A, 00560 Helsinki, Finland 3 Infineon Technologies AG , Wernerwerkstr. 2, 93049 Regensburg, Germany
Resume : As the progress and developments in wireless communication pushes the integration towards complete system-on-chip (SoC) units, Metal-Insulator-Metal (MIM) capacitors, which are one of the key passive elements in analog/mixed signal integrated circuits, have also to posses superior properties. According to the International Roadmap for Semiconductors (ITRS) for wireless communication technologies, the capacitance densities should and quality factors have to be increased, whereas capacitance-voltage variations and leakage currents should be minimized . These requirements imply the replacement of silicon oxide-based dielectrics with new high-k materials. Among a number of alternative materials that have been studied for MIM applications, SrTiO3 is one of the most promising candidates due to its high dielectric constant in crystalline phase. However, it is very hard to fulfill all the requirements raised by ITRS. We have previously reported that slightly Sr rich, 50 nm SrTiO3 thin films, grown by Atomic Layer Deposition (ALD) method, possessed a high dielectric constant of 95, but the leakage current density of TiN/SrTiO3/Au stacks was 10-3 A/cm2 at 1 V. Therefore, in this work we have applied high work function metal electrodes (Pt), in order to reduce the leakage currents of the SrTiO3 based MIM capacitors, since, it is known that electrical properties of MIM capacitors are not only dependent on the dielectric itself, but also on the bottom and the top electrodes. In addition, the effect of different post deposition anneals (performed in nitrogen or oxygen) on the structural and electrical properties of the SrTiO3 layers, will be presented.
|Session 10 : Paulo Santos|
|10:30||Si-compatible Device and Process Options for Graphene|
Authors : Max Christian Lemme
Affiliations : KTH Royal Institute of Technology
Resume : While benchmarking figures for graphene show remarkable properties like ballistic conductance over several hundred nanometers or charge carrier mobilities of several 100.000 cm2/Vs, integrated graphene devices are limited by defects in graphene and its dielectric environment. Furthermore, the lack of a band gap limits the applicability of graphene field effect transistors (GFETs) for logic applications. This talk will compare the RF performance of realistic graphene FETs with current silicon CMOS technology, paying particular attention to requirements concerning carrier mobility and contact resistance . In addition, a novel graphene-based hot electron transistor will be introduced: the graphene-base transistor (GBT) . This device has potential for RF operation as well as logic integration. Finally, graphene is an optoelectronic material and its application as a broadband photodetector will be discussed . The future manufacturability of graphene devices will depend on the availability of scalable graphene fabrication methods. Current state-of-the-art methods will therefore be discussed in terms of their applicability for co-integration with silicon technology. S. Rodriguez et al., "RF Performance Projections of Graphene FETs vs. Silicon MOSFETs", arXiv:1110.0978v1, 2011. W. Mehr et al., "Vertical Transistor with a Graphene Base", arXiv:1112.4520v1.  M.C. Lemme et al. "Gate-Activated Photoresponse in a Graphene p n Junction", Nano Lett., 11, 4134, 20
|11:00||1-Nanometer-Sized Active-Channel Molecular Quantum-Dot Transistor|
Authors : Elad D. Mentovich, Bogdan Belgorodsky, Itsik Kalifa, Shachar Richter
Affiliations : Nanoscience and Nanotechnology Institute, Tel Aviv University
Resume : The properties of a molecular quantum dot system are investigated using a novel structure of vertical molecular transistor. This C60-based device can be operated in two new modes: voltage-controlled switching and gate-controlled hysteresis. A polaron-based model is used to explain the operation of the transistor and to introduce some general rules for the construction of polaronic molecular transistors.
|11:15||From Si to SiC nanostructures|
Authors : L. Latu-Romain, M. Ollivier, A. Mantoux, M. Martin, and T. Baron
Affiliations : 1. Laboratoire des Technologies de la Microélectronique, (UMR5129 CNRS-UJF),17 av des Martyrs 38054 Grenoble, France 2. CEA, LETI, MINATEC, 17 av des Martyrs 38054 Grenoble, France ( 1 and 2 for all authors)
Resume : Among numerous materials, bulk silicon carbide is of great interest due to its superior physical and chemical properties: hardness, high thermal and chemical stability, biocompatibility, high breakdown electric field and electron drift velocity. It makes silicon carbide a material of choice for bio and gas-sensors. Moreover, the tremendous interest in nanoscale structures such as quantum dots (zero-dimension) and wires (quasi-one-dimension) stems from their size dependent properties. One-dimensional (1D) semiconductor nanostructures are of particular interest because of their potential applications in nanoscale electronic devices. Among various semiconductor materials, the growth of silicon nanowires has been extensively studied; however silicon has some disadvantages, it cannot be operated at high temperature, high power and high frequencies, and furthermore its biocompatibility and its chemical inertia is lower compare to silicon carbide. On another hand, the growth of SiC nanowires has been less studied, and the transport in silicon carbide nanowires keeps poor because of a low structural quality. In this context, Si nanowires networks can be obtained, but there is still a real challenge for such structure to be inert versus gases and biology. We propose here to present how a continuous protective shell of silicon carbide could be grown from Si nanowires and provides this function. By starting from single crystalline Si nanowires grown either by top-down or bottom-up approaches, silicon carbide has been obtained by carburization. The carburization is realized in a horizontal tube furnace at 1100°C during several minutes under methane diluted in hydrogen. In a first study, all the nanowire has been carburized, and it leads to the transformation from Si nanowire into SiC nanotube. A model of growth based on the outdiffusion of Si through the SiC layer was proposed to explain the transformation from Si nanowires to SiC nanotubes. This model was completed with thermodynamic calculations on the Si–H2–CH4–O2 system. In a second part, Si core /SiC shell nanowires have been elaborated. The pressure has been increased until atmospheric pressure and a very thin shell of silicon carbide has been grown all around the Si nanowires. In this case, the silicon carbide grown is cubic (3C-SiC) because of the growth temperature at 1100°C; the thickness varies from 2 nm to 4 nm depending on the carburization time. And finally, the silicon carbide layer is single crystalline and above all is continuous all around nanopillars. Original FIB-SEM preparation and TEM characterizations of these nano-objects will be presented. Silicon carbide may be used as a protective shell; these new nanomaterials (SiC nanotubes or Si/SiC core/shell nanowires) offer new possibilities for nano-electronics, bio- and gas-sensors.
|11:30||Multi-Scale Modelling of High-κ Deposition on Silicon Oxide; Link between Densification Mechanism and Interface Nanostructure|
Authors : C. Mastail1,2, A. Hemeryck1,2, A. Est?1,2, M. Djafari Rouhani1,2 and G. Landa1,2.
Affiliations : 1NRS; LAAS; 7 avenue du colonel Roche, F-31077 Toulouse, France 2Universit?e Toulouse ; UPS, INSA, INP, ISAE; UT1, UTM, LAAS ; F-31077 Toulouse, France
Resume : Miniaturizing components requires radical changes in the development of future micro-electronic devices. In this framework, the miniaturization of dielectric gates of MOS devices has become as thin as to be made permeable to leakage currents. Hafnium oxide is one of the promising high-κ substitutes for SiO2 as a gate oxide layer in future generations of MOS transistors. But at the required thicknesses, the structural and electronic properties of the gate oxide layer are strongly depending on the fabrication process. In order to gain a better understanding and control of the HfO2 fabrication process (Atomic Layer Deposition) we performed a multi-scale modelling based on a Monte Carlo Algorithm. The resulting software called “HIKAD” allows highlighting the link between the nano-structuration of the growth oxide layer and the deposition process in real experimental conditions. Going beyond rather obvious mechanisms, we indentified and implemented some densification mechanisms, which allow the evolution towards a massive material, starting from molecular precursors reactions. Thanks to these densifications mechanisms, the evolution of experimental structure observations (ie coverage, roughness and defect), and the deposited film composition will be discussed. The influence of the experimental growth conditions will be also qualitatively examined.
|11:45||Mechanical strain in the structure of the ensemble of silicon nanowires on a silicon substrate|
Authors : A. I. Klimovskaya 1, T. I. Kamins 2, 3, B. D. Shanina 1, P. M. Lytvyn 1, A. Nikolenko 1, A. V. Sarikov1, Yu. Yu. Kalashnik1
Affiliations : 1 V. Lashkarev Institute of Semiconductor Physics NAS Ukraine, 41 Nauki avenue, 03028 Kiev, Ukraine 2 Formerly with Hewlett Packard Laboratory, Palo Alto, CA 3 Currently with Department of Electrical Engineering, Stanford University, Stanford, CA
Resume : Great attention to the development of NEM devices, FETs and nanosensors based on application of nanowires grown on a substrate evokes interest to the mechanical and electronic properties of this system. In this report, we present the results of experimental study of the mechanical properties of the ensemble of silicon nanowires on a silicon substrate, which define a mode of device operation and play an important role in providing their stability and operating period. Experiment was carried out on the ensemble of silicon nanowires grown on boron-doped Si(100) and Si(111) substrates using the electron spin resonance, confocal micro-Raman spectroscopy, and electron beam induced conductivity. We showed that growing nanowires on a substrate by metal enhanced CVD technique gives rise to a strain both in the substrate and in the ensemble of nanowires resulting in the removal of the degeneration of the valence band in the point *k*=0 and the shift of the first order Raman peak at 520 cm-1 characteristic to the bulk silicon to the smaller energies. These results present experimental validation of a strong mutual interaction between a macro- (substrate) and nano- (wire) objects. Analysis of the results indicated the physical correlation between the shapes of nanocrystals and the energy structure of electron and phonon bands.
|Session 11 : Claudia Wiemer|
|14:00||High-frequency surface acoustic waves on silicon chips|
Authors : Paulo V. Santos1, A. D. de Barros1,3, P. D. Batista1,4, S. Rauwerdink1, K. Biermann1, B. Drescher1, W. Seidel1, A. Tahraoui1, Ch. Wenger2, U. Kaletta2, M. Fraschke2, D. Wolansky2, M. Kaynak2
Affiliations : 1 Paul-Drude-Institut für Festkörperelektronik, Hausvogteiplatz 5-7, D-10117 Berlin, Germany; 2 IHP, Im Technologiepark 25, D-15236 Frankfurt (Oder), Germany; 3 CCS-UNICAMP, Rua João Pandia Calógeras, 90, 13083-870 Campinas, SP, Brazil; 4 CBPF, Rua Dr. Xavier Sigaud, 150, 22290-180 Rio de Janeiro, Brazil
Resume : Surface acoustic wave (SAW) devices find applications in a wide range of fields including signal processing, light modulation, and sensors. In most cases, the SAWs are electrically generated using interdigital acoustic transducers (IDTs) deposited on a piezoelectric substrate. The monolithic fabrication of SAW devices on Si CMOS becomes possible via the deposition of thin piezoelectric films. In addition to more compact devices, monolithic fabrication can also take advantage of the high photolithographic resolution of standard silicon processing to produce high-frequency IDTs. Full integration of high-frequency SAW devices is normally hindered by the incompatibility of piezoelectric films with CMOS processing. Most of the approaches presented so far have been restricted to low frequencies (< 1 GHz). In this contribution, we demonstrate that efficient SAW elements operating at GHz frequencies can be integrated in a conventional Si CMOS process by taking full advantage of the high photo-lithographic resolution. In this process, the IDTs are embedded in a silicon dioxide layer, which is subsequently coated with a piezoelectric ZnO or AlN film. We show that SAWs delay lines fabricated using 200 nm metal lines can reach resonance frequencies up to 4 GHz. In addition to conventional applications, these devices can be used to explore functionalities associated with the transport of carriers by the SAW piezoelectric field. As an example, we show that optically excited electrons and holes can be transported over distance approaching 100 mum before been detected by a lateral pn-junction. These results open the way for the use of SAW for carrier control in CMOS structures.
|14:30||Rapid CMOS compatible ZnFe2O4 film deposition for enhanced inductance of integrated RF inductors.|
Authors : Ranajit Sai, Suresh D. Kulkarni, K. J. Vinoy, Navakanta Bhat, Srinivasrao A. Shivashankar
Affiliations : Ranajit Sai, Centre for Nano Science and Engineering, Indian Institute of Science, Bangalore, India; Suresh D. Kulkarni, Centre for Nano Science and Engineering, Indian Institute of Science, Bangalore, India; K. J. Vinoy, Electrical Communication Engineering, Indian Institute of Science, Bangalore, India; Navakanta Bhat, Centre for Nano Science and Engineering, Indian Institute of Science, Bangalore, India; Srinivasrao A. Shivashankar, Centre for Nano Science and Engineering, Indian Institute of Science, Bangalore, India
Resume : A lack of high performance integrated inductors has hindered the rapid development of the RFIC. An obvious solution to this problem is the use of magnetic materials with high permeability. Ferrite films are excellent candidates for RF devices due to their low cost, high resistivity and low eddy current losses. Nanocrystalline zinc ferrite thin film (ZFTF) exhibits novel magnetic properties suitable for RF applications. However, most ferrite film deposition processes require either high temperature or expensive equipment or both. We report a novel, microwave-assisted, low temperature (< 100°C) solution deposition process for obtaining high quality, polycrystalline ZFTFs on Si (100) and lithographed spiral inductor structures, within few minutes using safe solvents and precursors. The process is simple, rapid and scalable. A 15% enhancement in Inductance of the fabricated device was achieved due to the deposited ZFTF. Substantial inductance enhancement requires sufficiently thick films and our reported process is capable of depositing ~100 nm to ~20 µm thick films by altering the solution composition, without affecting the time and temperature. Beyond RFICs, ZFTF has applications in MRI, gas-sensing and photo-catalysis. Different applications require different surface morphology, which can be attained by tailoring the method reported here which, because of its low thermal budget, is compatible with modern CMOS, and its process flow.
|14:45||Synthesis and characterization of highly c-textured Al(1-x)Sc(x)N thin films in view of telecom applications|
Authors : M Moreira (a b), J.Bjurström (a), V.Yantchev (a), I.Katardjiev (a)
Affiliations : (a) Dept. Solid State Electronics, Ångström Lab., Uppsala University, Box 534, SE-751 21, Uppsala, Sweden; (b) Center for Semiconductor Components (CCS), University of Campinas, P.O. Box 6061, João Pandiá Calógeras 90, 13.083-870, Campinas-SP, Brazil
Resume : Wurtzite AlN is a piezoelectric material with excellent electro-acoustic properties and is used for the fabrication of high frequency thin film micro-acoustic components, most notably filters, duplexers, resonators, etc. Its moderate electromechanical coupling coefficient (kt2) of 6%-7% is insufficient for applications requiring larger bandwidths. Recent theoretical and experimental studies indicate that AlN alloyed with Sc exhibits a substantially higher piezoelectric constant than pure AlN. This study aims at determining the main electro-acoustic parameters of Al(1-x)Sc(x)N in view of large bandwidth applications. To this end, highly c-textured Al(1-x)Sc(x)N thin films have been synthesized with relative Sc concentrations of up to 0,15. Subsequently, FBAR resonators were fabricated and characterized as a function of the Sc content. It is seen that kt2 increases linearly with the latter to a value of 12% for a Sc concentration of x=0,15, while the Q value decreases from 739 to about 348 in the same concentration range. Likewise, the TCF varies from -35,9ppm/ºC to -39,8ppm/ºC, while the dielectric constant increases from ε=10 to a value of 14,1 for x=0,15. Finally, the relative dielectric losses are seen to increase by approximately a factor of two.
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